產(chǎn)品詳情：

SPI Interface Timing Requirements

Param Description Min Max Units
fSCLK SCLK frequency 100 ns delay inserted between address byte and data byte (single access), or between address and data, and between each data byte (burst access).
10
MHz
SCLK frequency, single access No delay between address and data byte 9 MHz
SCLK frequency, burst access No delay between address and data byte, or between data bytes 6.5 MHz
tsp,pd CSn low to positive edge on SCLK, in power-down mode 150 μs
tsp CSn low to positive edge on SCLK, in active mode 20 - ns
tch Clock high 50 - ns
tcl Clock low 50 - ns
trise Clock rise time - 5 ns
tfall Clock fall time - 5 ns
tsd Setup data (negative SCLK edge) to positive edge on SCLK (tsd applies between address and data bytes, and between data bytes) Single access 55 - ns
Burst access 76 - ns
thd Hold data after positive edge on SCLK 20 - ns
tns Negative edge on SCLK to CSn high 20 - ns